The core cells in some memory device types are based on NMOS field effect transistors and bit capacitors. The present inventor, Jack Peng, describes the conventional construction of one time programmable (OTP) memory cells in U.S. Pat. No. 6,667,902, issued Dec. 23, 2003. The circuit impedances are extremely high, and the capacitance values of the bit capacitors are very small. Spurious charges can be induced from nearby unintended sources causing the transistors to weakly turn on and their sense amplifiers to report a wrong data storage result.
Various circuits and methods have been developed in the prior art that apply clean up pulses in various ways to nullify the spurious charges on the floating nodes. Some of these add special circuits and more devices, substantially increasing the layout size and cost of the memory. Others apply the clean up pulses broadly and therefore this strategy demands higher power levels to support the cleanup operation that may not be possible in low power applications like passive UHF RFID tags.